The unclamped inductive switching test (UIS test) is used to evaluate avalanche capability of a semiconductor power device by measuring UIS current at breakdown voltage. Yet, failed site after UIS test always occur near edge of active area of semiconductor power device of prior art, as shown in FIG. 1A to FIG. 1C.
FIG. 1A shows the top view a trench MOSFET of prior art while FIG. 1B shows its a-a′ cross section view. Refer to FIG. 1B, this device is formed on N+ substrate 100 on which an N doped epitaxial layer 102 is grown. A plurality of trenches are etched inside said epitaxial layer 102 and filled with doped poly within trenches to serve as trench gates 104 over the gate oxide layer 108. Between each trench, there is a P-body region 112 introduced by Ion Implantation, and an N+ source regions 114 near the top surface of said P-body region 112. P+ region 106 is introduced underneath the source-body contact trench 105 which located penetrating through contact oxide interlayer lrce regions 114 to contact with the source regions 114 and the body regions 112.
As mentioned above, failed site always occur near edge of active area after UIS test, as shown in FIG. 1C, which is resulted from the turning on of a parasitic bipolar, as illustrated in FIG. 2A. Since the cells are most nearest gate metal pad and gate runner (refer to FIG. 1A), the gate of the cells near the active edge are turned on first when gate bias is increasing for turning on channel, resulting the parasitic bipolar turning on first near the active edge, thus weakening the avalanche capability of semiconductor device. Therefore, the measured UIS current at breakdown voltage is low and has wide distribution, as illustrated in FIG. 3.
Same technical difficulty also exists in conventional trench IGBT, as shown in FIG. 2B. Different from FIG. 2A the parasitic thyristor in trench IGBT is composed of an NPN and PNP bipolar as a result of the existence of P+ substrate 240.
Accordingly, it would be desirable to provide new and improved device configuration to enhance the avalanche capability of semiconductor devices.